Vaga de parceiro

Design Verification Engineer - São Paulo / SP

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Detalhes da Vaga

Bachelors or Masters Degree in Engineering (Electronics, Electrical, Telecom, or VLSI Engineering).
Roles And Responsibilities: As a member of the design verification team, your job is to break things.
You will work with logic designers to test RTL modules using UVM and have the opportunity to develop reusable verification components and testbenches.
If you thrive in a collaborative environment and enjoy learning new techniques for verification and tooling while working on machine learning acceleration hardware for Azure, then this is the position for you.
Responsible for the on-time delivery of block-level layouts, with acceptable quality.
You will develop testbench components and stimulus using System Verilog UVM libraries.
On a small, agile team, you will start from microarchitectural specifications and develop test environments and test plans to achieve code coverage targets.
You will collaborate via design reviews and code reviews.
Required Technical And Professional Expertise: Strong knowledge of Design & Verification methodologies (Times/Untimed SW Models), RTL IP, VIPs, UVM Env.
Understanding of verification tools like Simulator, Synthesis, etc.
Hands-on experience with C/C++, System Verilog, UVM, SystemC, RTL.
Understanding of standard protocol interfaces like AMBA, Automotive, PCIe, USB, etc.
Excellent written and verbal interpersonal skills.
Self-motivated and a great teammate.

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